DESIGN WITH DISCRETE TRANSISTORS

Updated: 12 Jan 2010
This page provides supplementary information to the chapter on Discrete Design in my book Small Signal Audio Design.
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SOME MORE ON THE 3-TRANSISTOR RIAA PREAMP CONFIGURATION

CONTENTS

INTRODUCTION
The circuit shown in Fig 1 is that given in the book. It was deliberately chosen as representative of contemporary practice in its era, and was not modified or optimised in any way. You will note that the single-rail supply is by modern standards low, at +15V; opamp-based preamplifiers would normally run from +/-15V, giving them a 6 dB headroom advantage at once.

Fig 1

The original preamplifier circuit

The circuit in Fig 1 is based on a smalle to the preamp, which is in the screening can to the right.

I built up the circuit with BC184 transistors, and was not exactly surprised that the performance was mediocre. The THD at 1 Vrms out (1 kHz) was 0.010%, which is a lot for such a low level. The distortion measurement was affected by a high level of hum at the output: -66 dBu at 50 Hz. Carefully screening the whole circuit only reduced this to -68 dBu, so electrostatic pickup was clearly not the major problem.

The RIAA equalisation accuracy is not good, which is only to be expected when you look at the standard component values in the RIAA network. Accurate RIAA networks do not have convenient component values. The errors reach +2.3 dB at 20 Hz and +0.7 dB at 20 kHz; the IEC amendment is apparently not implemented, as it would have given an extra attenuation of -3.0 dB at 20 Hz and -1.0 dB at 40 Hz.

Fig 2

The RIAA error

Pretty gross by today's standards

The preamplifier does not attempt to implement the IEC Amendment; the roll-off below 20 Hz is caused by C3. Increasing it from 47uF to 100uF much reduces the roll-off, as shown by the green trace here.

The preamplifier was being powered from a respectable bench PSU, but it still seemed possible that hum was getting in from the supply rail, as there is absolutely no filtering in the supply to Q1 collector. Inserting a 1K and 22uF filter in the path to R9 dropped the noise output -73.4 dBu. (This figure is the average of six readings, to reduce the tendency of a noise reading to jump about when there is significant low-frequency content. Measurement bandwidth is always 22 -22 kHz unless otherwise stated) A bandpass sweep of the noise output showed that there was now very little extra 50 Hz content. The RC filter gives an attenuation of -16.9 dB at 50 Hz and -22.8 dB at 100 Hz. Increasing the filter capacitance to 100uF however did give a slight improvement, so this was adopted; the attenuation at 50 Hz is now -29.9 dB.
Maximum output with the +15V rail was 3.4 Vrms at 1 kHz, (1% THD) and it is noticeable that clipping is not symmetrical, occurring first on the positive peaks. When this clipping does occur, there is a shift in the DC conditions of the circuit due to the way the biasing works.

Fig 3

THD with a +15V rail, at 1, 2, and 3 Vrms out.

Bandwidth 100Hz-80kHz

Fig 3 shows the distortion performance with a +15V rail, at 1, 2, and 3 Vrms out. (the input level is put through inverse-RIAA equalisation so that the output level remains constant with frequency) It was necessary to use the 100 Hz filter on the AP to get consistent results, despite having got rid of the 50 Hz problem, as there is still a large LF noise component due to the RIAA LF boost.

You can see that for 1 Vrms, thingsa aren't too bad. The mid-band distortion is around 0.01%, but there is a steady rise below 1 kHz. This is caused by the falling feedback factor as the RIAA curve demands more gain at lower frequencies. The other area of concern is at high frequencies; at 1 Vrms nothing too bad happens in the audio band, though THD has reached 0.02% at 20 kHz.
At the higher output level of 2 Vrms, the output stage starts to clip around 15 kHz, as Q2 can no longer drive the RIAA network with its falling impedance at high frequencies. Things are pretty gross at 3 Vrms out, with HF clipping starting at 4 kHz.

Clearly this RIAA preamp could use a bit of improvement. Let's see what can be done with it, concentrating at first on linearity and headroom.

INCREASING THE SUPPLY VOLTAGE TO +24V
The best bet for improving both linearity and headroom is to increase the supply voltage. We will start by turning it up to +24V, a voltage that can conveniently be obtained from a 7824 IC regulator. Fig 4 shows the results; distortion is somewhat reduced overall, and the HF overload problem has been pushed to slightly higher frequencies but the effect is not dramatic. The maximum output is now 3.8 Vrms at 1 kHz, (1% THD)which is not much of a return for increasing the supply voltage by 60%.

Fig 4

THD with a +24V rail, at 1, 2, and 3 Vrms out.

Bandwidth 100Hz-80kHz

Casting a jaundiced eye over the circuit, it's clear that it is still clipping assymmetrically. There is +18.4V on Q2 collector, which is too high for a symmetrical output swing. Rearranging the bias by changing R10 from 3K9 to 2K4 reduces Q2 collector volts to +15.0V, and gives much more output swing; maximum output is now 6.0 Vrms at 1 kHz, an improvement of 4 dB. While this does not give exact symmetry of clipping, it does seem to be close to optimal biasing for linearity. A good indication of this is that the distortion residual at 1 kHz is third-harmonic.
The distortion performance is transformed- 3 Vrms out (1 kHz) gives 0.06% in Fig 4. After re-biasing it has fallen to 0.014%, as in Fig 5. The HF overload effect has also been pushed out to above 20 kHz, even for the 3 Vrms case. Not bad for modifications that essentially cost nothing.

The improvement at lower output voltages is hard to see even with 100 Hz filtering because of the high noise output from a circuit with 50 dB of gain at low but unfiltered frequencies.

Fig 5

THD with a +24V rail, at 1, 2, and 3 Vrms out, after rebiasing.

Bandwidth 100Hz-80kHz

Considerable improvement in both distortion and HF overload behaviour

INCREASING THE SUPPLY VOLTAGE TO +30V
Since increasing the supply to +24V gave considerable benefits, we will increase it further to +30V. This increases the maximum output to 6.8 Vrms at 1 kHz, (1% THD) which is 6 dB up on the original circuit. R10 has been changed again to 2K2. The THD for the 1 Vrms case is completely submerged in low-frequency noise

Fig 6

THD with a +30V rail, at 1, 2, and 3 Vrms out, rebiased again.

Bandwidth 100Hz-80kHz for 3 and 2 Vrms, 400Hz-80kHz for 1 Vrms

HF overload behaviour has improved again, but HF distortion is rather worse. The LF distortion is notably improved.

NB This graph is at a slightly larger vertical scale than the previous ones.

As a side issue, we must consider how to generate the supply rail required. The 7824 IC regulator will accept a maximum input of 40V, so it is feasible to use that with the ADJ pin elevated by some means. For voltages above +30V this does not leave enough regulator headroom, and we might need to use the TL783 high-voltage regulator as described in the Chapter on power supplies.

GAIN DISTRIBUTION
At this point I began wondering what else could be done to reduce the distortion. There are practical limits to raising the supply voltage; power dissipation increases, and there is a danger that you could generate turn-on or turn-off transients that would damage stages downstream.

The configuration looks like two voltage amplifiers, and it seemed to be a good idea to find out how the open-loop gain is distributed between those two stages.

RUNNING THIS CONFIGURATION FROM DUAL SUPPLY RAILS
The question arises as to how easy it would be to convert this stage to run off dual supply rails, ie +/-V and 0V.

How does this configuration actually work? At first it looks like two voltage amplifiers, but

  1. A
  2. A l
  3. The

BIPOLAR JUNCTION TRANSISTORS. (BJTs)
It has taken a
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